1. Field of the Invention
The present invention relates to a semi-conductor booster circuit and more particularly to a semiconductor booster circuit, such as a charge pump circuit, which is used in an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory.
2. Description of the Related Art
In recent years, along with the promotion of a single 5V power supply or the promotion of a single 3V power supply for semiconductor integrated circuits such as EEPROMs and flash memories, the boosting has been performed in the integrated circuit. As a result, semiconductor booster circuits such as a Cockcroft Walton circuit and a charge pump circuit have been employed.
FIG. 18 shows a configuration of a conventional semiconductor booster circuit.
As shown in the figure, N-channel MOS transistors Q20 to Q24 are connected in cascade to configure a booster circuit having n stages. The gate terminals of the transistors Q20 to Q24 are connected to e respective source terminals N20 to N24 to which a clock signal φA or φB is input through respective capacitors C20 to C24.
As shown in FIG. 19, the clock signals φA and φB are in opposite phase with each other. Each of the clock signals φA and φB has a period of 1/f and an amplitude of Vφ. The clock signals φA and φB are obtained from a clock signal CK through two NAND circuits ND1 and ND2 and three inverters IV1 to IV3, and the amplitude Vφ thereof is equal to a power supply voltage Vdd. Incidentally, in FIG. 18, reference symbol G designates a ground terminal.
As shown in FIG. 18, in this semiconductor booster circuit, the power supply voltage Vdd is output as an input signal from a source terminal N27 of a transistor Q25, and an output voltage VPOUT is output as an output signal from an output terminal N26.
As described in an article “Analysis and Modeling of On-Chip High-voltage Generator Circuits for Use in EEPROM Circuits (IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 24, No. 5, October 1989) for example, the output voltage VPOUT of a sort of the semiconductor booster circuit is expressed by the following expressions:VPOUT=Vin−Vt+n([Vφ·[C/(C+Cs)−Vt]−IOUT/f(C+Cs)]  (1)Vt=Vt0+K2·([Vbs+22f)½−(2φf)½)  (2)where Vin is an input of the booster circuit, Vφ is an amplitude voltage of the clock signal, f is a clock frequency, C is a coupling capacitance to the clock signal, Cs is a parasitic capacitance in each of stages in the booster circuit, n is the number of stages of the booster circuit, VPOUT is the output voltage in the final stage of the booster circuit, IOUT is a load current in the output stage, Vto is a threshold voltage when a substrate bias is absent, Vbs is a substrate bias voltage (a potential difference between the source and a substrate or a well), φf is a Fermi potential, Vt is a threshold voltage of the transistor, and K2 is a substrate bias coefficient.
From the expression (1), it is understood that when the load current IOUT is zero and the relation of C/(C+Cs)=1 is established, the output voltage VPOUT is increased in proportion to both a value of (Vφ−Vt) and the number n of stages of the booster circuit. In the conventional booster circuit shown in FIG. 18, since the amplitude voltage Vφ of the clock signal is equal to the power supply voltage Vdd, the output voltage VPOUT is increased in proportion to both the value of (Vdd−Vt) and the number of stages of the booster circuit.
However, in the conventional booster circuit, there occurs a phenomenon that as the level of the output voltage VPOUT is increased, as shown in the expression (2), the threshold voltage Vt of each of the transistors Q20 to Q24 is increased due to the substrate effect.
Therefore, in the case where the stages of the booster circuit are discretely configured in order to prevent the substrate effect from occurring, the level of the output voltage VPOUT is increased in proportion to the number n of stages of the booster circuit. On the other hand, in the case where the transistors Q20 to Q24 are integrated to be formed on the same substrate, since the substrate effect occurs, as the number n of stages of the booster circuit is increased, the value of (Vdd−Vt) is decreased.
As a result, as shown in FIG. 20, along with the increasing of the number n of stages of the booster circuit, the output voltage VPOUT is decreased to a level lower than a value which is obtained when no substrate effect occurs, and is saturated at the point where the value of (Vdd−Vt) becomes zero. This means that no matter how the number n of stages of the booster circuit is increased, there is a limit in the resultant output voltage VPOUT. FIG. 21 shows the relationship between the power supply voltage Vdd and a maximum output voltage when the number n of stages of the booster circuit is made infinitely large. When the number n of stages of the booster circuit is made infinitely large, in the case where no substrate effect occurs, the resultant output voltage VPOUT becomes theoretically infinite. On the other hand, in the case where the substrate effect actually occurs, the resultant output voltage VPOUT is limited to a value depending on the power supply voltage Vdd. That is, in the conventional booster circuit; there arises a problem that in the case where the level of the power supply voltage Vdd is low, the desired output voltage VPOUT can not be obtained even if the number n of stages of the booster circuit is set to any large value.
For example, in the conventional booster circuit shown in FIG. 18, in the case where the power supply voltage Vdd is 2.5V, and the threshold voltage Vto is 0.6V when no substrate effect occurs (the substrate bias voltage is 0V), when the number n of stages of the booster circuit is set to 20, 20V can be obtained as the output voltage VPOUT. However, in the case where the power supply voltage Vdd is 2.0V, even if the number n of stages of the booster circuit is set to 100, only 12V can be obtained as the output voltage
On the other hand, in JP-A-61-254078, there is disclosed a Cockcroft type booster circuit in which a threshold voltage Vt of a MOS transistor in the subsequent stage having the substrate effect is made lower than that of a MOS transistor in the preceding stage, thereby improving the reduction of the output voltage due to the substrate effect.
However, in this configuration as well, the increase of the threshold voltage Vt due to the substrate effect can not be suppressed. For example, in the case where the level of the power supply voltage Vdd is approximately halved (Vdd=1 to 1.5V), even if the number n of stages of the booster circuit is set to any value, the desired output voltage VPOUT can not be obtained. In addition, since the threshold voltages Vt of the MOS transistors are set to a plurality of different levels, for example, it is necessary to conduct the extra process of photomask and ion implantation. As a result, the manufacturing process becomes complicated. This is a disadvantage.
FIG. 22 shows a configuration of still another conventional semiconductor booster circuit.
As shown in FIG. 22, eight N-channel MOS transistors M1 to M8 are connected in series with one another to configure a booster circuit having four stages. Gate terminals of the transistors M1 to M8 are connected to respective drain terminals (represented by nodes N0 to N7). To the drain terminals N0, N2, N4 and N6, a clock signal φA as shown in FIG. 17 is input through capacitors C1, C3, C5 and C7, respectively. To the drain terminals N1, N3, N5 and N7, a clock signal φB which is in opposite phase with the clock signal φA is input through capacitors C2, C4, C6 and C8, respectively. In addition, substrate terminals of the transistors M1 to M8 are connected to a ground terminal represented by a node N21). In addition, both a drain terminal and a gate terminal of each of the N-channel MOS transistors M20 and M21 are connected to an associated input terminal (represented by a node N20), and a substrate terminal thereof is connected to the ground terminal N21.
That is, the node N0 is respectively connected to the source terminal of the transistor M20, both the drain terminal and the gate terminal of the transistor M1, and one terminal of the capacitor C1. The node N1 is respectively connected to the source terminal of the transistor M21, both the drain terminal and the gate terminal of the transistor M2, the source terminal of the transistor M1 and one terminal of the capacitor C2. The node N2 is respectively connected to both the drain terminal and the gate terminal of the transistor M3, the source terminal of the transistor M2 and one terminal of the capacitor C3. The node N3 is respectively connected to both the drain terminal and the gate terminal of the transistor M4, the source terminal of the transistor M3 and one terminal of the capacitor C4. The node N4 is respectively connected to both the drain terminal and the gate terminal of the transistor M5, the source terminal of the transistor M4 and one terminal of the capacitor C5. The node N5 is respectively connected to both the drain terminal and the gate terminal of the transistor M6, the source terminal of the transistor M5 and one terminal of the capacitor C6. The node N6 is respectively connected to both the drain terminal and the gate terminal of the transistor M7, the source terminal of the transistor M6 and one terminal of the capacitor C7. In addition, the node N7 is respectively connected to both the drain terminal and the gate terminal of the transistor M8, the source terminal of the transistor M7 and one terminal of the capacitor C8. Further, an output terminal (represented by a node N8) of this semiconductor booster circuit is connected to the source terminal of the MOS transistor M8.
The above-mentioned expressions (1) and (2) are also applied to this booster circuit. Then, if the load current IOUT is zero, the capacitance ratio C/(C+Cs) is 1, and the amplitude voltage Vφ of the clock signal is equal to the power supply voltage Vdd in the expression (1), the voltage which is boosted per stage is expressed by (Vdd−Vt).
Therefore, it is understood that the output voltage VPOUT is influenced by the margin between the threshold voltage Vt of each of the MOS transistors and the power supply voltage Vdd. In particular, it is understood that when the relation of Vt≧Vdd is established, the boosting operation is not performed in the corresponding stage. That is, if the threshold voltage Vt is increased, the voltage which is boosted per stage becomes either small or zero. Therefore, even if the number n of stages of the booster circuit is increased, the output voltage VPOUT is hardly or never increased. For example, since the source potential of the MOS transistor shown in FIG. 22 is equal to the output voltage VPOUT, and the substrate potential is 0V, the substrate bias voltage Vbs is equal to the output voltage VPOUT. Now, since the booster circuit shown in FIG. 22 is provided for generating the positive high voltage, the output voltage VPOUT takes one of positive values. Therefore, the threshold voltage of the MOS transistor M8 becomes very high, and hence the boosting efficiency is reduced. This problem becomes especially pronounced during the low power source voltage operation in which the margin between the threshold voltage Vt and the power supply voltage Vdd is small.
In this booster circuit, as shown in FIG. 22, all the substrate terminals of the MOS transistors M1 to M8 are grounded. That is, the MOS transistors M1 to M8 are, as shown in FIG. 23, respectively constituted by sources/drains 454 to 462, which are formed in a P type semiconductor substrate 451, and gates 464 to 471, and the substrate terminal is connected to a ground terminal N21 through a P+ type impurity diffusion layer 452 in the semiconductor substrate 451. Incidentally, reference numeral 453 designates a drain of a MOS transistor 20 and reference numeral 463 designates a gate of the MOS transistor 20.
Therefore, there arises a problem that the potential of the source terminal of the MOS transistor, which is located in the more backward stage, becomes higher, and the difference in the potential between the source terminal and the substrate portion is increased so that due to the so-called substrate bias effect, the threshold voltage Vt is increased, and hence the output voltage VPOUT is limited due to the increase of the threshold voltage Vt.